The present invention relates to apparatus and methods for power conversion and, more particularly, to apparatus and methods for real time dynamic optimization of deadtime in power conversion circuits.
In modern power inverter/converter technology, a switching power device, such as an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET), is often utilized to convert direct-current (DC) power into alternating-current (AC) power. A pulse width modulated (PWM) method is widely adopted in switching pattern control.
In voltage source application, the deadtime period is used to ensure that there is sufficient delay before actually turning a switch ON so that it is not possible to have both devices conducting simultaneously, causing a shoot-through fault condition. Essentially, the deadtime period is an arbitrary way to determine when it is safe to turn ON a switch. Often, conventional systems will not have any measured value confirming that it is safe to turn ON and will rely solely on a worst case statistical means to make a decision. In conventional systems, the deadtime period is a fixed value of time which provides sufficient delay to accommodate the worst case conditions.
An example of a two switch phase-leg configuration including the ideal gating commands, for example pulse width modulation (PWM), is shown in FIG. 1, which forms the basic building block of many power electronic topologies for both DC/DC and DC/AC voltage source conversion. In this configuration, specifically the adjacency of upper switch 100 (S1) and lower switch 102 (S2), it is required that the switches 100, 102 never conduct simultaneously but rather in a complementary fashion, thus avoiding a potential short-circuit fault condition. The need for a time delay (commonly referred to as deadtime) between the upper and lower switch in a single phase-leg is justified because it reduces the chance both adjacent devices conduct simultaneously. Deadtime insertion is a common practice in the industry used avoid the potential of a short-circuit fault condition for voltage source applications and is typically implemented in the digital controller i.e., by inserting a fixed time delay on the rising edge of each gating commands as shown in FIG. 2.
Although deadtime insertion lowers the probability of a shoot-through fault, it introduces new characteristics into the system, such as: (a) low frequency harmonics (multiples of the fundamental waveform) which may decrease system efficiency and increase heat generated in the load, (b) nonlinearity which can cause sensorless control and flux estimation controller errors, and (c) decreased fundamental voltage.
There are many deadtime compensation techniques that have been widely reported in the open literature. Generally speaking, this type of solution involves a modification of the PWM signal for the purpose of producing an increased or decreased average voltage at the output (Vout). Although this type of solution has reported a reduction in the low frequency harmonics because of the effectiveness of their compensation methods; it is often not reported that a new problem is introduced, that the DC bus utilization has dropped to accommodate for the deadtime compensation method.
In the aerospace industry (for example), the DC bus utilization is vitally important as every opportunity to minimize weight and volume of the system components must be taken. It may not be acceptable for some sensitive applications to make use of deadtime compensation techniques which may lower the DC bus utilization. It is important to note that the method proposed here within does not suffer a large DC bus utilization impact.
As can be seen, there is a need for apparatus and methods for optimizing deadtime which may result in reduced low frequency harmonics, reduced nonlinearity and increased fundamental voltage.